In a conventional semiconductor integrated circuit for radio communication, each radio signal processing circuit is composed of a discrete component for each function block (such as an amplifier for signal amplification, a mixer for signal frequency conversion, a filter for passing only a signal of a desired bandwidth). However, with the recent improvements in semiconductor technology, a plurality of functional blocks configuring a radio signal processing circuit have been able to be incorporated in one semiconductor chip. A radio signal processing circuit with its components incorporated in one or more semiconductor chips converts a radio-frequency signal received from an antenna to a signal of a lower frequency band with high quality (with less noise or suppressing signals in bands other than a desired band).
To achieve a radio signal processing circuit at low cost, more functional blocks configuring the radio signal processing circuit have to be incorporated in one semiconductor chip. As one example of the radio signal processing circuit, a block diagram of a receiving circuit adopting a direct conversion system that has been examined as a background of the invention by the inventors of the present invention is shown in FIG. 4.
In FIG. 4, reference numeral 10 denotes a low noise amplifier (hereinafter, referred to as LNA) input terminal, 20 denotes an LNA, 30 denotes a filter, 40 denotes an orthogonal mixer, 41 and 42 denote mixers, 50 denotes a low frequency signal processing unit, 51 and 52 denote variable gain amplifiers, 53 and 54 denote filters, 60 and 61 denote output terminals, 100 denotes a clock signal oscillator, 110 and 120 denote clock signal buffers, 130 denotes a phase locked loop (hereinafter, referred to as PLL), 140 denotes a voltage controlled oscillator (hereinafter, referred to as VCO), 150 denotes a 90-degree phase shift circuit, 160 denotes a control signal input terminal, 170 denotes a control circuit, 1000 denotes a semiconductor chip, VCC denotes a power source, GND denotes a ground, CE1 and CE2 denote capacitors, and LE1 to LE4 denote transmission lines.
A radio signal inputted from an antenna (not shown) is inputted to the LNA input terminal 10. The LNA 20 amplifies the radio signal at low noise and low distortion characteristics to output the same. When the LNA 20 is set to have as high gain as possible within a range where distortion characteristics in a whole system of a receiving circuit can be satisfied, it is advantageous for low noise characteristics in the system of the receiving circuit. An output signal from the LNA 20 is inputted into the filter 30. An output from the filter 30 is inputted into the semiconductor chip 1000 again.
To achieve a radio signal processing circuit at low cost, more functional blocks configuring the radio signal processing circuit have to be incorporated in one semiconductor chip. In general, a surface acoustic wave (hereinafter referred to as SAW) filter, a dielectric filter or the like is used as the filter 30. Though signals in bands other than a desired band are suppressed by the filter 30, the SAW filter and the dielectric filter cannot be incorporated in a semiconductor chip. Accordingly, the filter 30 is disposed outside the semiconductor chip 1000.
A clock signal generated from the clock signal generator 100 is inputted into the semiconductor chip 1000 and it is amplified by the clock signal buffers 110 and 120 and then supplied to the PLL 130 and the control circuit 170. The control circuit 170 performs gain switching among the LNA 20 and the variable gain amplifiers 51 and 52 and setting of a frequency dividing ratio in the PLL 130 according to a control signal inputted from the control signal input terminal 160.
The gain switching in the LNA 20 to a lower gain occurs when a signal level of a radio signal inputted from the antenna (not shown) into the LNA input terminal 10 is high enough to deteriorate the distortion characteristics in the system of the signal receiving circuit positioned at a downstream side of the filter 30. On the contrary, the gain switching in the LNA 20 to a higher gain occurs when a signal level of a radio signal inputted from the antenna (not shown) into the LNA input terminal 10 is not high enough to influence the distortion characteristics in the system of the signal receiving circuit positioned at a downstream side of the filter 30. In this manner, the noise characteristics and the distortion characteristics in the system of the receiving circuit become optimal.
The gain switching in the variable gain amplifiers 51 and 52 is performed so that levels of signals outputted from the output terminals 60 and 61 fall in a signal level range set by a demodulating circuit (not shown) disposed at downstream sides of the output terminals 60 and 61.
The PLL 130 compares a frequency of a signal obtained by dividing an oscillation frequency of the VCO 140 by a frequency dividing ratio set according to a control signal from the control circuit 170 and a frequency of a signal obtained by dividing a frequency of a clock signal from the clock signal buffer 120 by a frequency dividing ratio set according to a control signal from the control circuit 170 with each other and performs the control so that a difference therebetween becomes a desired level or less. By this means, an output voltage which determines the oscillation frequency of the VCO 140 is outputted to the VCO 140.
For example, when the clock signal frequency from the clock signal buffer 120 is represented as fR, the frequency dividing ratio set according to a control signal from the control circuit 170 for the clock signal frequency from the clock signal buffer 120 is represented as R, and the frequency dividing ratio set according to a control signal from the control circuit 170 for the oscillation frequency from the VCO 140 is represented as N, an oscillation frequency fVCO of the VCO 140 is expressed by the following equation.fVCO=fR×N/R 
By this means, the VCO 140 is controlled to oscillate at different frequencies according to respective receiving channels. Since the signal receiving circuit shown in FIG. 4 is of the direct conversion system, the center frequency of a receiving channel and a frequency of an oscillation signal provided to the mixers 41 and 42 are controlled to be equal to each other.
The oscillation signals from the VCO 140 are inputted to the mixer 41 and the mixer 42. In this case, the oscillation signal inputted into the mixer 41 has the same phase as the original oscillation signal and the oscillation signal inputted into the mixer 42 is converted by the 90-degree phase shift circuit 150 so as to have a phase different from that of the signal inputted into the mixer 41 by 90 degrees. An output signal from the mixer 41 is amplified to a desired level by the variable gain amplifier 51, and after signal components of the amplified output signal in bands other than a desired channel band are suppressed by the filter 53, the signal is outputted from the output terminal 60. An output signal from the mixer 42 is amplified to a desired level by the variable gain amplifier 52, and after signal components in the amplified output signal in bands other than a desired channel band are suppressed by the filter 54, the signal is outputted from the output terminal 61.
The mixers 41 and 42 are collectively called “orthogonal mixer” and they are shown as an orthogonal mixer 40 in FIG. 4. The variable gain amplifiers 51 and 52 and the filters 53 and 54 perform processing of a low frequency signal in a desired channel band obtained by the frequency conversion by the orthogonal mixer 40 and they are shown as a low frequency signal processing unit 50 in FIG. 4.
The power source VCC is a power source which supplies power to the semiconductor chip 1000. The power is inputted into the semiconductor chip 1000 via the transmission lines LE1 to LE4. The capacitor CE2 is inserted between the LNA 20 and the power source and the capacitor CE1 is inserted between the clock signal buffers 110 and 120 and the power source, so that characteristic degradation and malfunction due to noise or the like can be suppressed by short-circuiting the impedance of the power source VCC which rises due to the influence of the transmission lines LE1 to LE4 in an AC manner.